1. Field of the Invention
This invention relates to a bus compression device for reducing or compressing the number of bit signals representing parallel data. This invention is also directed to a bus decompression device for extending the number of bit signals representing compressed parallel data. Further, this invention relates to a data interface employing a bus compressing method and to a liquid crystal display using the data interface.
2. Description of the Prior Art
Since the transmission of audio information many years ago, higher band or capacity signals containing text information, video information and the like have been transmitted using various bus interfaces to transmit signals containing substantially more information than the audio information. The text information, video information and the like occupy a high frequency band and require many transmission lines. As the frequency band for the information and the number of transmission lines increase, an electromagnetic interference(EMI) increases between the transmission lines. The EMI problem is common in a data bus. In order to reduce the EMI in the transmission line, line matchers have been usually added to the transmission line. However, such line matcher complicates a wiring structure of the transmission line and limits the system design.
For example, as shown in FIG. 1, a computer system employing a liquid crystal display(LCD) includes various kinds of couplers LM1 to LM5 provided between a video card 12 in a computer body 10 and data driver integrated circuits D-ICs 24 in an LCD 20. Specifically, twenty-eight first line matchers LM1 corresponding to a 18-bit first bus 11 and a 10-bit first control bus 13 are arranged between the video card 12 and a first cable connector 16. Eighteen second matchers LM2 and ten third matchers LM3 respectively corresponding to a 18-bit second bus and a 10-bit control bus 23 are arranged between a second cable connector 18 and a controller 26. Finally, thirty-six fourth line matcher LM4 and seven fifth line matchers LM5 corresponding to a thirty-six bit third bus 35 and a seven bit third control bus are arranged between the controller 26 and the D-ICs 24.
As shown in FIG. 2, each line matcher LM1 includes a resistor R1, a capacitor C1 and an inductor L1 which are connected in the T shape. As shown in FIG. 3, each line matcher LM2 includes a resistor R1, a capacitor C2 and two inductors L2 and L3. As shown in FIG. 4, each line matcher LM3 includes an inductor L4 and a resistor R3. Each line matcher LM4 includes a resistor R4 and a capacitor C3 as shown in FIG. 5. The line matcher LM5 includes an inductor L5, a resistor R5 and a capacitor C4.
The matchers LM1 to LM5 match an impedance and eliminate high frequency and/or low frequency components, thereby suppressing an occurrence of EMI. As a result, the data passing through the flexible printed circuit (FPC) cable 16 and the first to third data buses 11, 21 and 25 and the clock and timing signals transmitted through the FPC cable 16 and the first to third control buses 13, 23 and 27 are not influenced by the EMI.
As described above, in the conventional computer system having a number of line matchers installed in the transmission line extending from the video card in the computer body to the D-ICs in the LCD, the configuration thereof becomes complicated and the design thereof is limited due to the line matchers. Also, the conventional computer system requires as many transmission lines as the number of data bits.
Furthermore, as the number of picture elements or pixels in the liquid crystal panel increase above the XGA format, the data bus installed between the controller and the D-ICs must have a dual structure due to a response speed of the D-ICs. In this case, the circuit configuration of the LCD having a wiring structure becomes more complicated and a die arranged with the D-ICs must be enlarged.